Implementations of translation lookaside buffers (TLBs) are well known in the art of computer designs and FIG. 1 illustrates a typical block diagram of a TLB configuration within a computer. As shown in FIG. 1, during an execution cycle of a computer, a virtual address is typically supplied via virtual address bus 73 from an execution unit (not shown) of the computer to TLB 70. One or more tag entries from a tag RAM array 71 (also referred to as a tag vector array) selected by the received virtual address is provided to an array of virtual address comparators 72. Each address comparator in comparator array 72 generates an output tag compare bit indicating whether a tag entry match is detected for an associated tag entry in tag RAM array 71. Typically, the output compare bit of the comparator corresponds to a logical "1" whenever a tag entry match is detected between the tag entry and the virtual address. Comparator array 72 thus generates a n-bit tag compare signal 74 indicating a collective result of comparing the one or more selected tag entries of tag vector array 71 to the virtual address.
N-bit tag compare signal 74 is coupled to a physical address RAM array 82 (also referred to as PA vector array) to select a corresponding physical address 78 to be supplied as an output of PA array 82. Thus, when an active address translation cycle signal 86 from a TLB control unit (not shown) is provided to PA array 82, additional control logic in that array enables selected physical address 78 to be available at the output of PA array 82 so to be placed onto a physical address bus 84, thereby providing that address to other devices of the computer, such as a main memory device.
A direct mapped TLB, a set associative TLB, and a fully associative TLB are examples of common types of TLB implementations. In both the set associative TLB and the fully associative TLB, the virtual address is typically supplied to multiple entries of the tag vector array rather than a single tag entry as is in a direct mapped TLB. A problem that occurs with set associative and fully associative TLB implementations is that, occasionally, a matching virtual address is detected in more than one tag entry of the TLB. The detection of more than one matching tag entry results in multiple selected TLB physical address vectors contending for access to the physical address bus to the main memory. This contention for the same bus could result not only in placing a corrupted address onto the bus, but also causing some of the selected PA vectors to be overwritten by other simultaneously selected PA vectors.
U.S. Pat. No. 5, 237,671 ("the '671 Patent") describes a TLB shutdown circuit that uses an analog comparator to determine when a multiple tag entry match occurs by detecting the voltage variation in a pull-up line that is coupled to every output in an array of virtual address comparators. However, because the voltage difference between a one tag entry match and a two tag entry match is difficult to detect, the TLB shutdown circuit of the '671 Patent is designed to detect a voltage difference between when a one tag entry match occurs and when greater than five tag entry matches occur. A single tag entry match indicates normal TLB operation, while greater than five tag entry matches signifies an addressing error and triggers the generation of a TLB shutdown signal. But since data corruption and error can result when even two matching tag entries occur, there is therefore a need to provide means for detecting whenever two or more matching TLB tag entries occur, and to indicate a TLB address translation error on such occasions.